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  • Jun 04, 2019 News!IJMMM Vol.7, No.3 has been published with online version.   [Click]
General Information
    • ISSN: 1793-8198 (Print)
    • Abbreviated Title: Int. J. Mater. Mech. Manuf.
    • Frequency: Bimonthly
    • DOI: 10.18178/IJMMM
    • Editor-in-Chief: Prof. K. M. Gupta; Prof. Ian McAndrew
    • Executive Editor: Cherry L. Chen
    • Abstracting/Indexing: EI (INSPEC, IET), Chemical Abstracts Services (CAS),  ProQuest, Crossref, Ulrich's Periodicals Directory,  EBSCO.
    • E-mail ijmmm@ejournal.net

Editor-in-chief
Prof. Ian McAndrew
Capitol Technology University, USA
It is my honor to be the editor-in-chief of IJMMM. I will do my best to work with the editorial team and help make this journal better.

IJMMM 2019 Vol.7(3): 144-149 ISSN: 1793-8198
DOI: 10.18178/ijmmm.2019.7.3.448

Comparison study of Dual Material Gate Silicon on Insulator junctionless Transistor and with Junction Transistor for Analog Performance

S. C. Wagaj and S. C. Patil
Abstract—In this paper compare analog performance parameters of dual material gate silicon on Insulator iunctionless transistor (DMG SOI JLT) and DMG SOI Transistor. In this paper analog parameters as like transconductance (gm), transconductance generation factor (gm/IDS), output conductance (gd), intrinsic gain (gm/gd) , intrinsic gate delay, intrinsic static power dissipation and cut off frequency. It has been observed that transconductance, transconductance generation factor, output conductance, intrinsic gain, intrinsic gate delay, intrinsic static power dissipation and cut off frequency of DMG SOI JLT improved by 12%, 29%, 69%, 21%, 5%,26% and 3% respectively over the DMG SOI Transistor. It has been observed that due to work function difference of dual material gate improves the electrostatic control on channel and on current also improved by 34% over the DMG SOI Transistor. The DMG SOI JLT is the best candidate for low power device performance.

Index Terms—Dual material gate, junctionless transistor, intrinsic delay, silicon on insulator.

The authors are with JSPM’s Rajarshi Shahu College of Engineering, Pune Savitribai Phule Pune University, Pune, India (e-mail: scwagaj@yahoo.com, shailaja.rscoe@gmail.com).

[PDF]

Cite: S. C. Wagaj and S. C. Patil, "Comparison study of Dual Material Gate Silicon on Insulator junctionless Transistor and with Junction Transistor for Analog Performance," International Journal of Materials, Mechanics and Manufacturing vol. 7, no. 3, pp. 144-149, 2019.

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