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General Information
    • ISSN: 1793-8198 (Print)
    • Abbreviated Title: Int. J. Mater. Mech. Manuf.
    • Frequency: Bimonthly
    • DOI: 10.18178/IJMMM
    • Editor-in-Chief: Prof. Ian McAndrew
    • Co-editor-in-Chief: Prof. K. M. Gupta
    • Executive Editor: Cherry L. Chen
    • Abstracting/Indexing: Inspec (IET), Chemical Abstracts Services (CAS),  ProQuest, Crossref, Ulrich's Periodicals Directory,  EBSCO.
    • E-mail ijmmm@ejournal.net

Prof. Ian McAndrew
Capitol Technology University, USA
It is my honor to be the editor-in-chief of IJMMM. I will do my best to work with the editorial team and help make this journal better.

IJMMM 2020 Vol.8(3): 143-147 ISSN: 1793-8198
DOI: 10.18178/ijmmm.2020.8.3.497

Chip Architecture for Silicon Characterization of Foundry Kit Standard Cells

Siddharth Katare, Ajay Kumar Gautam, Victor John, Rohini V Meti, and Manoj Chitneedi
Abstract—Standard cell libraries are an integral part of converting an RTL to a manufacturable physical design. The automatic place and route EDA tools use these characterized standard cell libraries to arrive at an optimal design within given constraints. The correlation between characterized data and the actual behaviour of cells on Silicon is critical for meeting the desired performance of the manufactured chip. In this paper, we present a modular design and measurement method which can be implemented in an ASIC for correlating the characteristics of the standard cell library. This method simplifies the design of the package and the test board and relatively simple test equipment can be used to measure the silicon characteristics. The ASIC presented in this paper was designed in 180nm for characterizing standard cells, which are delivered as part of the foundry design kit.

Index Terms—Standard cell libraries, characterization, silicon correlation, validation.

The authors are with Sankalp Semiconductor Pvt ltd, Bangalore, India (e-mail: siddharth.katare@sankalpsemi.com, ajay.gautam@sankalpsemi.com, victor.john@sankalpsemi.com, rohini.meti@sankalpsemi.com, manoj.chitneedi@sankalpsemi.com)


Cite: Siddharth Katare, Ajay Kumar Gautam, Victor John, Rohini V Meti, and Manoj Chitneedi, "Chip Architecture for Silicon Characterization of Foundry Kit Standard Cells," International Journal of Materials, Mechanics and Manufacturing vol. 8, no. 3, pp. 143-147, 2020.

Copyright © 2020 by the authors. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
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